1. Field of the Invention
The invention relates to a signal processor with a processor module having address, data and control inputs and outputs, including an interrupt signal input for receiving an incoming interrupt request signal. Such devices, particularly if equipped with so-called microprocessors as signal processor modules, are increasingly used in systems in which two or more processor modules are working together: multiprocessor systems. In such a system, it is of the utmost importance that interrupt requests are processed in such a way that the operation of the system itself is affected as little as possible. The interrupt mechanism of well-known microprocessors operates as follows: upon receipt of an interrupt request signal at the interrupt signal input, the microprocessor will complete the current instruction after which the interrupt request will be processed.
When a processor module in a multiprocessor system wishes to communicate with one or more processor modules, this may take place in the following obvious manner: an individual interrupt request signal line runs from each processor module to all other processor modules. The required processor module is then interrupted by energizing the appropriate line. The obvious disadvantage of this method is that the number of interrupt request signal lines increases almost quadratically (n.(n-1)) with the number of processor modules. Therefore, this solution is not acceptable in practice.
2. Description of the Prior Art
A conventional solution is known from "Electronics" of 20th Jan. 1977, page 107, FIG. 8, in which use is made of only one interrupt request signal line which is common to all processor modules. As soon as a particular processor module makes an interrupt request, all other processor modules will be interrupted. The interrupt vector (which is specifically the destination address corresponding to the interrupt request) which is applied to the system bus by said processor module, is compared with the identities of the receiving processor modules by means of a program routine loaded into these processor modules.
Each of the processor modules then decides whether the interrupt request is intended for it. A great disadvantage of this procedure is that, at the start of each communication, all processor modules are temporarily obstructed in their progress: the program routine for the above-mentioned comparison causes the processor modules temporarily to interrupt their normal operation.